[llvm-bugs] [Bug 36669] [llvm-mca][x86] Teach how to identify instructions that perform partial register updates.

via llvm-bugs llvm-bugs at lists.llvm.org
Thu Nov 8 10:09:49 PST 2018


Andrea Di Biagio <andrea.dibiagio at gmail.com> changed:

           What    |Removed                     |Added
         Resolution|---                         |FIXED
             Status|CONFIRMED                   |RESOLVED

--- Comment #2 from Andrea Di Biagio <andrea.dibiagio at gmail.com> ---
This is fixed by the following commit:


This allows users to describe registers that are renamed by a processor
register file.

Partial writes to registers that are not part of any "renamable" register class
have a false dependency on a previous definition of the underlying register.

If a partial write implicitly clears a super register, then it doesn't cause
partial register stalls.
That has been fixed by revision 

"[llvm] r335113 - [llvm-mca][X86] Teach how to identify register writes that
implicitly clear the upper portion of a super-register."

We still don't correctly model merge opcodes which are generated on reads of
partially written register. This mostly affects Intel processors, where some
partial writes can be renamed, but cause a merge opcode to be issued on a
pipeline when the super-register is read.

You are receiving this mail because:
You are on the CC list for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-bugs/attachments/20181108/4359a4f8/attachment-0001.html>

More information about the llvm-bugs mailing list