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<body><span class="vcard"><a class="email" href="mailto:andrea.dibiagio@gmail.com" title="Andrea Di Biagio <andrea.dibiagio@gmail.com>"> <span class="fn">Andrea Di Biagio</span></a>
</span> changed
<a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - [llvm-mca][x86] Teach how to identify instructions that perform partial register updates."
href="https://bugs.llvm.org/show_bug.cgi?id=36669">bug 36669</a>
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<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>What</th>
<th>Removed</th>
<th>Added</th>
</tr>
<tr>
<td style="text-align:right;">Resolution</td>
<td>---
</td>
<td>FIXED
</td>
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<td style="text-align:right;">Status</td>
<td>CONFIRMED
</td>
<td>RESOLVED
</td>
</tr></table>
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<b><a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - [llvm-mca][x86] Teach how to identify instructions that perform partial register updates."
href="https://bugs.llvm.org/show_bug.cgi?id=36669#c2">Comment # 2</a>
on <a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - [llvm-mca][x86] Teach how to identify instructions that perform partial register updates."
href="https://bugs.llvm.org/show_bug.cgi?id=36669">bug 36669</a>
from <span class="vcard"><a class="email" href="mailto:andrea.dibiagio@gmail.com" title="Andrea Di Biagio <andrea.dibiagio@gmail.com>"> <span class="fn">Andrea Di Biagio</span></a>
</span></b>
<pre>This is fixed by the following commit:
<a href="http://llvm.org/viewvc/llvm-project?view=revision&revision=337123">http://llvm.org/viewvc/llvm-project?view=revision&revision=337123</a>
This allows users to describe registers that are renamed by a processor
register file.
Partial writes to registers that are not part of any "renamable" register class
have a false dependency on a previous definition of the underlying register.
If a partial write implicitly clears a super register, then it doesn't cause
partial register stalls.
That has been fixed by revision
<a href="http://llvm.org/viewvc/llvm-project?view=revision&revision=335113">http://llvm.org/viewvc/llvm-project?view=revision&revision=335113</a>
"[llvm] r335113 - [llvm-mca][X86] Teach how to identify register writes that
implicitly clear the upper portion of a super-register."
We still don't correctly model merge opcodes which are generated on reads of
partially written register. This mostly affects Intel processors, where some
partial writes can be renamed, but cause a merge opcode to be issued on a
pipeline when the super-register is read.</pre>
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