[llvm-bugs] [Bug 37568] New: [llvm-exegesis] Latency test code breaking register dependencies

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=37568

            Bug ID: 37568
           Summary: [llvm-exegesis] Latency test code breaking register
                    dependencies
           Product: new-bugs
           Version: unspecified
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: llvm-dev at redking.me.uk
                CC: andrea.dibiagio at gmail.com, clement.courbet at gmail.com,
                    craig.topper at gmail.com, gchatelet at google.com,
                    greg.bedwell at sony.com, llvm-bugs at lists.llvm.org,
                    matthew.davis at sony.com

I'm seeing llvm-exegesis report a number of instructions give far too fast
latency values as they are repeating source registers, which permits breaking
register dependencies in the frontend, this is most commonly for cases that are
guaranteed to generate zero/allbits results.

Search Agner (http://www.agner.org/optimize/microarchitecture.pdf) for
"Breaking dependency chains" and "Dependency-breaking instructions", these
instruction types include:

X86 Instructions:
XOR
SUB
SBB(depends on carry flag only) 
CMP

MMX/SSE/AVX Instructions:
PXOR/XORPS/XORPD
PANDN/ANDNPS/ANDNPD
PSUBx
PCMPEQx/PCMPGTx

Depending on the CPU this might include MMX/AVX1/AVX2 variants as well.

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