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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [llvm-exegesis] Latency test code breaking register dependencies"
href="https://bugs.llvm.org/show_bug.cgi?id=37568">37568</a>
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<th>Summary</th>
<td>[llvm-exegesis] Latency test code breaking register dependencies
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<th>Product</th>
<td>new-bugs
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<th>Version</th>
<td>unspecified
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<th>Hardware</th>
<td>PC
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<th>OS</th>
<td>Windows NT
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>new bugs
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>llvm-dev@redking.me.uk
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<th>CC</th>
<td>andrea.dibiagio@gmail.com, clement.courbet@gmail.com, craig.topper@gmail.com, gchatelet@google.com, greg.bedwell@sony.com, llvm-bugs@lists.llvm.org, matthew.davis@sony.com
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<pre>I'm seeing llvm-exegesis report a number of instructions give far too fast
latency values as they are repeating source registers, which permits breaking
register dependencies in the frontend, this is most commonly for cases that are
guaranteed to generate zero/allbits results.
Search Agner (<a href="http://www.agner.org/optimize/microarchitecture.pdf">http://www.agner.org/optimize/microarchitecture.pdf</a>) for
"Breaking dependency chains" and "Dependency-breaking instructions", these
instruction types include:
X86 Instructions:
XOR
SUB
SBB(depends on carry flag only)
CMP
MMX/SSE/AVX Instructions:
PXOR/XORPS/XORPD
PANDN/ANDNPS/ANDNPD
PSUBx
PCMPEQx/PCMPGTx
Depending on the CPU this might include MMX/AVX1/AVX2 variants as well.</pre>
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