[llvm-bugs] [Bug 37386] New: [X86] Scalar masked load/store instrinsics require a 512-bit vector

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=37386

            Bug ID: 37386
           Summary: [X86] Scalar masked load/store instrinsics require a
                    512-bit vector
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: craig.topper at gmail.com
                CC: llvm-bugs at lists.llvm.org

These intrinsics are implemented with an extend to 512 bits and a use of a
512-bit target independent masked load/store intrinsic

_mm_mask_store_ss
_mm_mask_store_sd
_mm_mask_load_ss
_mm_maskz_load_ss
_mm_mask_load_sd
_mm_maskz_load_sd


They are very specifically pattern matched to MOVSS/MOVSD in isel.

If we started making progress with the prefer vector width stuff, this will
become a problem as these intrinsics will force the frontend to believe a
512-bit vector is needed.

-- 
You are receiving this mail because:
You are on the CC list for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-bugs/attachments/20180508/65edfbbf/attachment.html>