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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [X86] Scalar masked load/store instrinsics require a 512-bit vector"
href="https://bugs.llvm.org/show_bug.cgi?id=37386">37386</a>
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<th>Summary</th>
<td>[X86] Scalar masked load/store instrinsics require a 512-bit vector
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Windows NT
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: X86
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>craig.topper@gmail.com
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<p>
<div>
<pre>These intrinsics are implemented with an extend to 512 bits and a use of a
512-bit target independent masked load/store intrinsic
_mm_mask_store_ss
_mm_mask_store_sd
_mm_mask_load_ss
_mm_maskz_load_ss
_mm_mask_load_sd
_mm_maskz_load_sd
They are very specifically pattern matched to MOVSS/MOVSD in isel.
If we started making progress with the prefer vector width stuff, this will
become a problem as these intrinsics will force the frontend to believe a
512-bit vector is needed.</pre>
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