[llvm-bugs] [Bug 37324] New: In SchedMachineModel, specifying SchedWrite in ReadAdvance doesn't work.

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=37324

            Bug ID: 37324
           Summary: In SchedMachineModel, specifying SchedWrite in
                    ReadAdvance doesn't work.
           Product: libraries
           Version: 6.0
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Target Description Classes
          Assignee: unassignedbugs at nondot.org
          Reporter: swpenim at gmail.com
                CC: llvm-bugs at lists.llvm.org

I want to write a ReadAdvance that will only be applied to a SchedWrite. After
specifying it in ReadAdvance, it doesn't work.

For example, 
We have a 4-cycle latency from a LDRi12 to MLA in cortexR52 on Arm backend with
function foo.

int foo(int *p) {
  return p[0] * p[1] + p[2];
}

If I change ARMScheduleR52.td as follows:

-def : ReadAdvance<R52Read_ISS, 0>;
+def : ReadAdvance<R52Read_ISS, 1, [R52WriteLd]>;

and move definition of R52WriteLd earlier, we can find the latency is still the
same.

But if I remove R52WriteLd in ReadAdvance, the latency is reduced to 3.

-- 
You are receiving this mail because:
You are on the CC list for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-bugs/attachments/20180503/27846b34/attachment.html>