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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - In SchedMachineModel, specifying SchedWrite in ReadAdvance doesn't work."
href="https://bugs.llvm.org/show_bug.cgi?id=37324">37324</a>
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<th>Summary</th>
<td>In SchedMachineModel, specifying SchedWrite in ReadAdvance doesn't work.
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<th>Product</th>
<td>libraries
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<th>Version</th>
<td>6.0
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Linux
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Target Description Classes
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>swpenim@gmail.com
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<p>
<div>
<pre>I want to write a ReadAdvance that will only be applied to a SchedWrite. After
specifying it in ReadAdvance, it doesn't work.
For example,
We have a 4-cycle latency from a LDRi12 to MLA in cortexR52 on Arm backend with
function foo.
int foo(int *p) {
return p[0] * p[1] + p[2];
}
If I change ARMScheduleR52.td as follows:
-def : ReadAdvance<R52Read_ISS, 0>;
+def : ReadAdvance<R52Read_ISS, 1, [R52WriteLd]>;
and move definition of R52WriteLd earlier, we can find the latency is still the
same.
But if I remove R52WriteLd in ReadAdvance, the latency is reduced to 3.</pre>
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</p>
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