[llvm-bugs] [Bug 36924] New: [X86] Split vector schedule classes by vector width only as necessary

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=36924

            Bug ID: 36924
           Summary: [X86] Split vector schedule classes by vector width
                    only as necessary
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: llvm-dev at redking.me.uk
                CC: andrea.dibiagio at gmail.com, clement.courbet at gmail.com,
                    craig.topper at gmail.com, llvm-bugs at lists.llvm.org,
                    spatel+llvm at rotateright.com
            Blocks: 36908

Many targets have different schedule costs for 128/256/512-bit rr and rm
versions of various SSE instructions (e.g. WriteFADD:
ADDSS/ADDPS/VADDPS/VADDPSY/VADDPSZ).

Given that we're overriding them anyhow means that we will generate multiple
scheduler class entries so we should probably just create separate schedule
classes for them.

But, similar to [Bug #35608], it'd be useful to avoid having to define all
these classes for cases where they don't differ or are not supported - so some
kind of default inheritence would be very useful.

e.g.

WriteFADD_SSE : WriteFADD
WriteFADD_AVX128 : WriteFADD
WriteFADD_AVX256 : WriteFADD
WriteFADD_AVX512 : WriteFADD

Or maybe some mechanism with SchedAlias, or could we introduce something like
SchedDefaultAlias?


Referenced Bugs:

https://bugs.llvm.org/show_bug.cgi?id=36908
[Bug 36908] [meta][x86] Improve scheduler classes instruction coverage
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