[llvm-bugs] [Bug 36908] New: [meta][x86] Improve scheduler classes instruction coverage

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=36908

            Bug ID: 36908
           Summary: [meta][x86] Improve scheduler classes instruction
                    coverage
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: llvm-dev at redking.me.uk
                CC: llvm-bugs at lists.llvm.org
        Depends on: 32857, 35587, 35608, 36881
            Blocks: 32325

We've tended to avoid introducing too many scheduler classes, especially as not
all targets need to support them [Bug #35608].

However, we could considerably reduce the number of custom InstRW entries if we
were smarter about the instructions attached to each class - adding/splitting
classes, etc.


Referenced Bugs:

https://bugs.llvm.org/show_bug.cgi?id=32325
[Bug 32325] [META][X86] Improve implementation and use of X86 scheduler models
https://bugs.llvm.org/show_bug.cgi?id=32857
[Bug 32857] Add scheduler classes for vector masked load/store operations
https://bugs.llvm.org/show_bug.cgi?id=35587
[Bug 35587] [X86] Scheduler information missing for CRC32 instructions on
haswell, broadwell, skylake
https://bugs.llvm.org/show_bug.cgi?id=35608
[Bug 35608] [X86] Remove Schedule classes from models that don't use them
https://bugs.llvm.org/show_bug.cgi?id=36881
[Bug 36881] [X86] TZCNT/LZCNT/BSR/BSF have weird SchedRW
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