[llvm-bugs] [Bug 36890] New: [X86] WriteRMW should require a AGU port for the store.

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=36890

            Bug ID: 36890
           Summary: [X86] WriteRMW should require a AGU port for the
                    store.
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: craig.topper at gmail.com
                CC: llvm-bugs at lists.llvm.org

This comment which appears in all the Intel scheduler models is incorrect

// A folded store needs a cycle on port 4 for the store data, but it does not
// need an extra port 2/3 cycle to recompute the address.
def : WriteRes<WriteRMW, [SKLPort4]>;


The load uop and the store address uop are separate micro ops. There address
computation isn't shared between them. You can see this in Agner's tables where
RMW add shows 4 unfused uops. Load, add, store address, and store data.

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