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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [X86] WriteRMW should require a AGU port for the store."
href="https://bugs.llvm.org/show_bug.cgi?id=36890">36890</a>
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<th>Summary</th>
<td>[X86] WriteRMW should require a AGU port for the store.
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<th>Product</th>
<td>libraries
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<th>Version</th>
<td>trunk
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<th>Hardware</th>
<td>PC
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: X86
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>craig.topper@gmail.com
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<p>
<div>
<pre>This comment which appears in all the Intel scheduler models is incorrect
// A folded store needs a cycle on port 4 for the store data, but it does not
// need an extra port 2/3 cycle to recompute the address.
def : WriteRes<WriteRMW, [SKLPort4]>;
The load uop and the store address uop are separate micro ops. There address
computation isn't shared between them. You can see this in Agner's tables where
RMW add shows 4 unfused uops. Load, add, store address, and store data.</pre>
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