[llvm-bugs] [Bug 36794] New: [MISched] indeterministic effects of enabling bidirectional scheduling pre-RA
via llvm-bugs
llvm-bugs at lists.llvm.org
Mon Mar 19 04:18:30 PDT 2018
https://bugs.llvm.org/show_bug.cgi?id=36794
Bug ID: 36794
Summary: [MISched] indeterministic effects of enabling
bidirectional scheduling pre-RA
Product: libraries
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: enhancement
Priority: P
Component: Common Code Generator Code
Assignee: unassignedbugs at nondot.org
Reporter: paulsson at linux.vnet.ibm.com
CC: llvm-bugs at lists.llvm.org
Created attachment 20090
--> https://bugs.llvm.org/attachment.cgi?id=20090&action=edit
reduced testcase (1 spill more bidirectional)
I found a test case where enabling bidirectional scheduling increased the
number of spilled live ranges. I reduced this to a small test case (attached),
and found to my surprise that even when bidirectional produces the same final
schedule for a region, it may give different slot indexes if it was picked from
Top, like:
BOTTOM-UP BIDIRECTIONAL
2080B CallBRASL @strchr, $r2d, $r 2080B CallBRASL @strchr, $r2d, $r
2112B %81:gr64bit = COPY $r2d | 2088B %81:gr64bit = COPY $r2d
2120B ADJCALLSTACKUP 0, 0 | 2096B ADJCALLSTACKUP 0, 0
2160B %82:gr64bit = IMPLICIT_DEF 2160B %82:gr64bit = IMPLICIT_DEF
I suspect that this change in slot indexes causes the register allocator to
produce a different result based on interval weighting etc.
Is this something that should be fixed? When experimenting with pre-RA
scheduling it is of course desirable to reduce side effects like this, I think.
bin/llc -mtriple=s390x-linux-gnu -mcpu=z13 -o out.s ./tc1.ll --stats |& grep
"spilled live ranges"
4 regalloc - Number of spilled live ranges
bin/llc -mtriple=s390x-linux-gnu -mcpu=z13 -o out.s ./tc1.ll --stats
-misched-topdown=false -misched-bottomup=false |& grep "spilled live ranges"
5 regalloc - Number of spilled live ranges
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