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      <base href="https://bugs.llvm.org/">
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    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - [MISched] indeterministic effects of enabling bidirectional scheduling pre-RA"
   href="https://bugs.llvm.org/show_bug.cgi?id=36794">36794</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>[MISched] indeterministic effects of enabling bidirectional scheduling pre-RA
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>libraries
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>Linux
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>enhancement
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Common Code Generator Code
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>paulsson@linux.vnet.ibm.com
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>llvm-bugs@lists.llvm.org
          </td>
        </tr></table>
      <p>
        <div>
        <pre>Created <span class=""><a href="attachment.cgi?id=20090" name="attach_20090" title="reduced testcase (1 spill more bidirectional)">attachment 20090</a> <a href="attachment.cgi?id=20090&action=edit" title="reduced testcase (1 spill more bidirectional)">[details]</a></span>
reduced testcase (1 spill more bidirectional)

I found a test case where enabling bidirectional scheduling increased the
number of spilled live ranges. I reduced this to a small test case (attached),
and found to my surprise that even when bidirectional produces the same final
schedule for a region, it may give different slot indexes if it was picked from
Top, like:

BOTTOM-UP                               BIDIRECTIONAL
2080B     CallBRASL @strchr, $r2d, $r   2080B     CallBRASL @strchr, $r2d, $r
2112B     %81:gr64bit = COPY $r2d     | 2088B     %81:gr64bit = COPY $r2d
2120B     ADJCALLSTACKUP 0, 0         | 2096B     ADJCALLSTACKUP 0, 0
2160B     %82:gr64bit = IMPLICIT_DEF    2160B     %82:gr64bit = IMPLICIT_DEF

I suspect that this change in slot indexes causes the register allocator to
produce a different result based on interval weighting etc.

Is this something that should be fixed? When experimenting with pre-RA
scheduling it is of course desirable to reduce side effects like this, I think.


bin/llc -mtriple=s390x-linux-gnu -mcpu=z13 -o out.s ./tc1.ll --stats |& grep
"spilled live ranges"
  4 regalloc              - Number of spilled live ranges

bin/llc -mtriple=s390x-linux-gnu -mcpu=z13 -o out.s ./tc1.ll --stats
-misched-topdown=false -misched-bottomup=false |& grep "spilled live ranges"
  5 regalloc              - Number of spilled live ranges</pre>
        </div>
      </p>


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