[llvm-bugs] [Bug 35094] [AArch64] atomicrmw on Armv8.1-a memory ordering can be changed
via llvm-bugs
llvm-bugs at lists.llvm.org
Thu Mar 8 07:10:34 PST 2018
https://bugs.llvm.org/show_bug.cgi?id=35094
Oliver Stannard <oliver.stannard at arm.com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Resolution|--- |INVALID
Status|NEW |RESOLVED
CC| |oliver.stannard at arm.com
--- Comment #1 from Oliver Stannard <oliver.stannard at arm.com> ---
I've discussed this with Christof, and we don't think this is a bug. It only
matters that a load is ordered before a "fence acquire" if the load has some
observable effect, which can't happen if the destination register is ZR. The
architecture does still specify that there is an ordering edge between the load
and the store done by the LD<OP>.
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