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<body><span class="vcard"><a class="email" href="mailto:oliver.stannard@arm.com" title="Oliver Stannard <oliver.stannard@arm.com>"> <span class="fn">Oliver Stannard</span></a>
</span> changed
<a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED INVALID - [AArch64] atomicrmw on Armv8.1-a memory ordering can be changed"
href="https://bugs.llvm.org/show_bug.cgi?id=35094">bug 35094</a>
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<th>What</th>
<th>Removed</th>
<th>Added</th>
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<td style="text-align:right;">Resolution</td>
<td>---
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<td>INVALID
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<td style="text-align:right;">Status</td>
<td>NEW
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<td>RESOLVED
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<td style="text-align:right;">CC</td>
<td>
</td>
<td>oliver.stannard@arm.com
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<b><a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED INVALID - [AArch64] atomicrmw on Armv8.1-a memory ordering can be changed"
href="https://bugs.llvm.org/show_bug.cgi?id=35094#c1">Comment # 1</a>
on <a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED INVALID - [AArch64] atomicrmw on Armv8.1-a memory ordering can be changed"
href="https://bugs.llvm.org/show_bug.cgi?id=35094">bug 35094</a>
from <span class="vcard"><a class="email" href="mailto:oliver.stannard@arm.com" title="Oliver Stannard <oliver.stannard@arm.com>"> <span class="fn">Oliver Stannard</span></a>
</span></b>
<pre>I've discussed this with Christof, and we don't think this is a bug. It only
matters that a load is ordered before a "fence acquire" if the load has some
observable effect, which can't happen if the destination register is ZR. The
architecture does still specify that there is an ordering edge between the load
and the store done by the LD<OP>.</pre>
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