[llvm-bugs] [Bug 37989] New: [DAGCombine] Call TargetLowering::SimplifyDemandedVectorElts from supported ops

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=37989

            Bug ID: 37989
           Summary: [DAGCombine] Call
                    TargetLowering::SimplifyDemandedVectorElts from
                    supported ops
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Common Code Generator Code
          Assignee: unassignedbugs at nondot.org
          Reporter: llvm-dev at redking.me.uk
                CC: andrea.dibiagio at gmail.com, craig.topper at gmail.com,
                    efriedma at codeaurora.org, filcab at gmail.com,
                    lebedev.ri at gmail.com, llvm-bugs at lists.llvm.org,
                    spatel+llvm at rotateright.com

As mentioned on [Bug #37890], we currently only use SimplifyDemandedVectorElts
in the DAGCombiner DAGCombiner::visitVECTOR_SHUFFLE.

We should add support/tests for calling from DAGCombiner::vist* for all the
supported vector ops:

ISD::CONCAT_VECTORS
ISD::INSERT_SUBVECTOR (and add ISD::EXTRACT_SUBVECTOR support)
ISD::INSERT_VECTOR_ELT (and call from DAGCombiner::visitEXTRACT_VECTOR_ELT)
ISD::VSELECT

Other possible useful operations to add include the various ISD::*EXTEND ops
and we should support passthrough handling of the same AND/OR/XOR/ADD/SUB/MUL
(+SHL/SRL/SRA?) operations as InstCombiner::SimplifyDemandedVectorElts.

Once those are in place we can start adding any necessary target opcodes
through SimplifyDemandedVectorEltsForTargetNode etc.

-- 
You are receiving this mail because:
You are on the CC list for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-bugs/attachments/20180629/f49dd7b0/attachment.html>