[llvm-bugs] [Bug 37749] New: [X86][AVX] Use of 256-bit bitwise operations in 256-bit integer math

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=37749

            Bug ID: 37749
           Summary: [X86][AVX] Use of 256-bit bitwise operations in
                    256-bit integer math
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: llvm-dev at redking.me.uk
                CC: craig.topper at gmail.com, llvm-bugs at lists.llvm.org,
                    spatel+llvm at rotateright.com

https://godbolt.org/g/QjounZ

AVX1 has to split 256-bit vector integer math, but as it has legal 256-bit
bitwise ops it sometimes decides to concat the 128-bit values back together to
perform the op, just to split again straight after.

It'd be much better if everything happened at 128-bits at least for the
constant mask case (possibly for others):

#include <x86intrin.h>
__v8si mask_and(__v8si x, __v8si y, __v8si z) {
  __v8si m = (__v8si) {255, 255, 255, 255, 255, 255, 255, 255};
  return (((x + y) & m) + z);
}

define <8 x i32> @_Z8mask_andDv8_iS_S_(<8 x i32>, <8 x i32>, <8 x i32>) {
  %4 = add <8 x i32> %1, %0
  %5 = and <8 x i32> %4, <i32 255, i32 255, i32 255, i32 255, i32 255, i32 255,
i32 255, i32 255>
  %6 = add <8 x i32> %5, %2
  ret <8 x i32> %6
}

_Z8mask_andDv8_iS_S_: # @_Z8mask_andDv8_iS_S_
  vextractf128 $1, %ymm0, %xmm3
  vextractf128 $1, %ymm1, %xmm4
  vpaddd %xmm0, %xmm1, %xmm0
  vpaddd %xmm3, %xmm4, %xmm3
  vinsertf128 $1, %xmm3, %ymm0, %ymm0
  vandps .LCPI0_0(%rip), %ymm0, %ymm0
  vextractf128 $1, %ymm2, %xmm3
  vextractf128 $1, %ymm0, %xmm1
  vpaddd %xmm2, %xmm0, %xmm0
  vpaddd %xmm3, %xmm1, %xmm1
  vinsertf128 $1, %xmm1, %ymm0, %ymm0
  retq

Oddly in the godbolt example I'm seeing this just for AND, not the OR/XOR
cases:

_Z7mask_orDv8_iS_S_: # @_Z7mask_orDv8_iS_S_
  vpaddd %xmm0, %xmm1, %xmm3
  vextractf128 $1, %ymm0, %xmm0
  vextractf128 $1, %ymm1, %xmm1
  vextractf128 $1, %ymm2, %xmm4
  vpaddd %xmm0, %xmm1, %xmm0
  vmovdqa .LCPI1_0(%rip), %xmm1 # xmm1 = [1095216660735,1095216660735]
  vpor %xmm1, %xmm0, %xmm0
  vpor %xmm1, %xmm3, %xmm1
  vpaddd %xmm4, %xmm0, %xmm0
  vpaddd %xmm2, %xmm1, %xmm1
  vinsertf128 $1, %xmm0, %ymm1, %ymm0
  retq

_Z8mask_xorDv8_iS_S_: # @_Z8mask_xorDv8_iS_S_
  vpaddd %xmm0, %xmm1, %xmm3
  vextractf128 $1, %ymm0, %xmm0
  vextractf128 $1, %ymm1, %xmm1
  vextractf128 $1, %ymm2, %xmm4
  vpaddd %xmm0, %xmm1, %xmm0
  vmovdqa .LCPI2_0(%rip), %xmm1 # xmm1 = [1095216660735,1095216660735]
  vpxor %xmm1, %xmm0, %xmm0
  vpxor %xmm1, %xmm3, %xmm1
  vpaddd %xmm4, %xmm0, %xmm0
  vpaddd %xmm2, %xmm1, %xmm1
  vinsertf128 $1, %xmm0, %ymm1, %ymm0
  retq

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