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<base href="https://bugs.llvm.org/">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [X86][AVX] Use of 256-bit bitwise operations in 256-bit integer math"
href="https://bugs.llvm.org/show_bug.cgi?id=37749">37749</a>
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<th>Summary</th>
<td>[X86][AVX] Use of 256-bit bitwise operations in 256-bit integer math
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
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<th>Hardware</th>
<td>PC
</td>
</tr>
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<th>OS</th>
<td>Windows NT
</td>
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<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>enhancement
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
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<th>Component</th>
<td>Backend: X86
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>llvm-dev@redking.me.uk
</td>
</tr>
<tr>
<th>CC</th>
<td>craig.topper@gmail.com, llvm-bugs@lists.llvm.org, spatel+llvm@rotateright.com
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<p>
<div>
<pre><a href="https://godbolt.org/g/QjounZ">https://godbolt.org/g/QjounZ</a>
AVX1 has to split 256-bit vector integer math, but as it has legal 256-bit
bitwise ops it sometimes decides to concat the 128-bit values back together to
perform the op, just to split again straight after.
It'd be much better if everything happened at 128-bits at least for the
constant mask case (possibly for others):
#include <x86intrin.h>
__v8si mask_and(__v8si x, __v8si y, __v8si z) {
__v8si m = (__v8si) {255, 255, 255, 255, 255, 255, 255, 255};
return (((x + y) & m) + z);
}
define <8 x i32> @_Z8mask_andDv8_iS_S_(<8 x i32>, <8 x i32>, <8 x i32>) {
%4 = add <8 x i32> %1, %0
%5 = and <8 x i32> %4, <i32 255, i32 255, i32 255, i32 255, i32 255, i32 255,
i32 255, i32 255>
%6 = add <8 x i32> %5, %2
ret <8 x i32> %6
}
_Z8mask_andDv8_iS_S_: # @_Z8mask_andDv8_iS_S_
vextractf128 $1, %ymm0, %xmm3
vextractf128 $1, %ymm1, %xmm4
vpaddd %xmm0, %xmm1, %xmm0
vpaddd %xmm3, %xmm4, %xmm3
vinsertf128 $1, %xmm3, %ymm0, %ymm0
vandps .LCPI0_0(%rip), %ymm0, %ymm0
vextractf128 $1, %ymm2, %xmm3
vextractf128 $1, %ymm0, %xmm1
vpaddd %xmm2, %xmm0, %xmm0
vpaddd %xmm3, %xmm1, %xmm1
vinsertf128 $1, %xmm1, %ymm0, %ymm0
retq
Oddly in the godbolt example I'm seeing this just for AND, not the OR/XOR
cases:
_Z7mask_orDv8_iS_S_: # @_Z7mask_orDv8_iS_S_
vpaddd %xmm0, %xmm1, %xmm3
vextractf128 $1, %ymm0, %xmm0
vextractf128 $1, %ymm1, %xmm1
vextractf128 $1, %ymm2, %xmm4
vpaddd %xmm0, %xmm1, %xmm0
vmovdqa .LCPI1_0(%rip), %xmm1 # xmm1 = [1095216660735,1095216660735]
vpor %xmm1, %xmm0, %xmm0
vpor %xmm1, %xmm3, %xmm1
vpaddd %xmm4, %xmm0, %xmm0
vpaddd %xmm2, %xmm1, %xmm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
retq
_Z8mask_xorDv8_iS_S_: # @_Z8mask_xorDv8_iS_S_
vpaddd %xmm0, %xmm1, %xmm3
vextractf128 $1, %ymm0, %xmm0
vextractf128 $1, %ymm1, %xmm1
vextractf128 $1, %ymm2, %xmm4
vpaddd %xmm0, %xmm1, %xmm0
vmovdqa .LCPI2_0(%rip), %xmm1 # xmm1 = [1095216660735,1095216660735]
vpxor %xmm1, %xmm0, %xmm0
vpxor %xmm1, %xmm3, %xmm1
vpaddd %xmm4, %xmm0, %xmm0
vpaddd %xmm2, %xmm1, %xmm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
retq</pre>
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