[llvm-bugs] [Bug 38389] New: ARM: LLVM generates invalid VSTM instruction

via llvm-bugs llvm-bugs at lists.llvm.org
Tue Jul 31 09:28:46 PDT 2018


            Bug ID: 38389
           Summary: ARM: LLVM generates invalid VSTM instruction
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: ARM
          Assignee: unassignedbugs at nondot.org
          Reporter: jyknight at google.com
                CC: llvm-bugs at lists.llvm.org

Still working on reducing a small test-case, will attach when I have one.

Compiling a particular C++ file with:
  clang --target=arm-linux-androideabi -O2 -march=armv7-a -mfpu=neon
results in an error message from the GNU assembler:
  Error: register list must contain at least 1 and at most 16 registers --

Checking the docs
indeed it says that the "list must contain at least one register. If it
contains doubleword registers it must not contain more than 16 registers."  So
the complaint from GNU as is correct.

It appears that ARMLoadStoreOptimizer.cpp does not have any code restricting it
to merging only up to 16 double-word registers.

Also, unfortunately, building with -fintegrated-as "works" -- it doesn't
complain, but rather simply encodes the invalid instruction with 18 registers.
I don't know what that actually ends up doing on hardware, but I imagine
probably not something good. :) LLVM's assembler ought to refuse to encode the
invalid instruction also.

The same restriction exists also for VLDM.

You are receiving this mail because:
You are on the CC list for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-bugs/attachments/20180731/977c44b5/attachment.html>

More information about the llvm-bugs mailing list