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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - ARM: LLVM generates invalid VSTM instruction"
href="https://bugs.llvm.org/show_bug.cgi?id=38389">38389</a>
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<th>Summary</th>
<td>ARM: LLVM generates invalid VSTM instruction
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
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<th>Version</th>
<td>trunk
</td>
</tr>
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<th>Hardware</th>
<td>PC
</td>
</tr>
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<th>OS</th>
<td>Linux
</td>
</tr>
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<th>Status</th>
<td>NEW
</td>
</tr>
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<th>Severity</th>
<td>normal
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
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<th>Component</th>
<td>Backend: ARM
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
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<th>Reporter</th>
<td>jyknight@google.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
</tr></table>
<p>
<div>
<pre>Still working on reducing a small test-case, will attach when I have one.
Compiling a particular C++ file with:
clang --target=arm-linux-androideabi -O2 -march=armv7-a -mfpu=neon
-fno-integrated-as
results in an error message from the GNU assembler:
Error: register list must contain at least 1 and at most 16 registers --
`vstmia
r0,{d13,d14,d15,d16,d17,d18,d19,d20,d21,d22,d23,d24,d25,d26,d27,d28,d29,d30}'
Checking the docs
<<a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/CHDCBGAE.html">http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/CHDCBGAE.html</a>>,
indeed it says that the "list must contain at least one register. If it
contains doubleword registers it must not contain more than 16 registers." So
the complaint from GNU as is correct.
It appears that ARMLoadStoreOptimizer.cpp does not have any code restricting it
to merging only up to 16 double-word registers.
Also, unfortunately, building with -fintegrated-as "works" -- it doesn't
complain, but rather simply encodes the invalid instruction with 18 registers.
I don't know what that actually ends up doing on hardware, but I imagine
probably not something good. :) LLVM's assembler ought to refuse to encode the
invalid instruction also.
The same restriction exists also for VLDM.</pre>
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