[llvm-bugs] [Bug 38151] New: [X86][SSE] Investigate ISD::MULHU for ISD::SRL lowering

via llvm-bugs llvm-bugs at lists.llvm.org
Thu Jul 12 08:37:44 PDT 2018


            Bug ID: 38151
           Summary: [X86][SSE] Investigate ISD::MULHU for ISD::SRL
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: llvm-dev at redking.me.uk
                CC: andrea.dibiagio at gmail.com, craig.topper at gmail.com,
                    efriedma at codeaurora.org, lebedev.ri at gmail.com,
                    llvm-bugs at lists.llvm.org, spatel+llvm at rotateright.com

Similar to what we do for rotation lowering, we should be able to use
ISD::MULHU (PMULHUW etc.) to perform vector logical shift right.

We already do something similar for ISD::SHL, except in this case I think we'd
need to treat zero shift elements as a special (pass-through) case.

Constant amounts should be a definite gain (at least for v16i8/v8i16) -
benchmarking would be necessary to determine if non-constant values are worth

Similarly, ISD::SRA might be able to use ISD::MULHS but I haven't investigated

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