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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [X86][SSE] Investigate ISD::MULHU for ISD::SRL lowering"
href="https://bugs.llvm.org/show_bug.cgi?id=38151">38151</a>
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<th>Summary</th>
<td>[X86][SSE] Investigate ISD::MULHU for ISD::SRL lowering
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<th>Product</th>
<td>libraries
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
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<th>OS</th>
<td>Windows NT
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: X86
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>llvm-dev@redking.me.uk
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<th>CC</th>
<td>andrea.dibiagio@gmail.com, craig.topper@gmail.com, efriedma@codeaurora.org, lebedev.ri@gmail.com, llvm-bugs@lists.llvm.org, spatel+llvm@rotateright.com
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<p>
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<pre>Similar to what we do for rotation lowering, we should be able to use
ISD::MULHU (PMULHUW etc.) to perform vector logical shift right.
We already do something similar for ISD::SHL, except in this case I think we'd
need to treat zero shift elements as a special (pass-through) case.
Constant amounts should be a definite gain (at least for v16i8/v8i16) -
benchmarking would be necessary to determine if non-constant values are worth
it.
Similarly, ISD::SRA might be able to use ISD::MULHS but I haven't investigated
this.</pre>
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