[llvm-bugs] [Bug 36014] New: Assertion `MI && "No instruction at index"' with unallocatable inline assembly

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=36014

            Bug ID: 36014
           Summary: Assertion `MI && "No instruction at index"' with
                    unallocatable inline assembly
           Product: new-bugs
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: pablo.barrio at arm.com
                CC: llvm-bugs at lists.llvm.org

Created attachment 19709
  --> https://bugs.llvm.org/attachment.cgi?id=19709&action=edit
Inline assembly using too many registers

The attached code features some inline assembly code that tries to use more
registers than available. This code tries to use a subset of the GPRs for the
allocation of the first register via constraint 'h' (higher subset of the
GPRs), hitting an assertion in the register allocator:

llvm/lib/CodeGen/SplitKit.cpp:772: llvm::SlotIndex
llvm::SplitEditor::leaveIntvAfter(llvm::SlotIndex): Assertion `MI && "No
instruction at index"' failed.

Using constraint 'r' instead (i.e. general-purpose register) for all the
registers results in the following message shown several times:

error: inline assembly requires more registers than available

which is the correct behaviour.

I was able to track down why allocating to the all-GPRs class gives a
reasonable error message, while high/low GPRs crash the compiler. Function
RAGreedy::tryInstructionSplit() bails out at the beginning if the register
class being used for the allocation is not a "proper subclass":

  if (!RegClassInfo.isProperSubClass(CurRC))
    return 0;

If I understood correctly, proper subclasses have a parent class with a bigger
number of available allocatable registers. The Arm GPR class is not a proper
subclass, while the "low regs GPR" class is (with GPR being its parent class
with a bigger number of regs). Therefore, GPRs don't hit the bug later in that
function, whereas subclasses do.

The following command can be used to build the example:

clang --target=thumb-arm-none-eabi -march=armv8-m.main -O2 test.c

I have been able to reproduce with Arm, but I believe this bug will affect any
architecture with constraints that select register classes with parent classes.

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