[llvm-bugs] [Bug 35965] New: TableGen doesn't constrain temporary registers

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https://bugs.llvm.org/show_bug.cgi?id=35965

            Bug ID: 35965
           Summary: TableGen doesn't constrain temporary registers
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: GlobalISel
          Assignee: unassignedbugs at nondot.org
          Reporter: diana.picus at linaro.org
                CC: llvm-bugs at lists.llvm.org

Created attachment 19683
  --> https://bugs.llvm.org/attachment.cgi?id=19683&action=edit
Reproducer: llc -mtriple armv7-gnueabihf -global-isel
-debug-only=instruction-select [...]

When trying to select this pattern (ARMInstrVFP.td):
def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)),
                   (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;

We get:
[...]
Selecting: 
  %1:gprb(s32) = G_FPTOSI %0(s32)
Into:
  %2:_(s32) = VTOSIZS %0(s32), 14, %noreg
  %1:gpr(s32) = COPY %2(s32)
[...]
LLVM ERROR: VReg has no regclass after selection (in function: test_fptosi)

Note: In order to reproduce, you'll have to mark G_FPTOSI as legal in
ARMLegalizerInfo.cpp (since I haven't committed that part yet):
setAction({G_FPTOSI, s32}, Legal);
setAction({G_FPTOSI, 1, s32}, Legal);

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