[llvm-bugs] [Bug 35836] New: Assertion `ARM::GPRRegClass.contains(DestReg, SrcReg) && "Thumb1 can only copy GPR registers"' failed.

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=35836

            Bug ID: 35836
           Summary: Assertion `ARM::GPRRegClass.contains(DestReg, SrcReg)
                    && "Thumb1 can only copy GPR registers"' failed.
           Product: libraries
           Version: 6.0
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: ARM
          Assignee: unassignedbugs at nondot.org
          Reporter: efriedma at codeaurora.org
                CC: llvm-bugs at lists.llvm.org, renato.golin at linaro.org,
                    roger.ferreribanez at arm.com
            Blocks: 35804

I think this is a regression from r320355 ([ARM] Use ADDCARRY / SUBCARRY).  It
looks like the SelectionDAG scheduler generates a schedule where an ADDS and an
ADC aren't adjacent, and tries to COPY cpsr to compensate. But we have no way
to lower that because we don't have access to MSR/MRS in Thumb1 mode, so we get
an assertion failure.  Haven't really thought through the right way to fix
this.

Testcase (crashes with "llc test.ll"):

target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv5e-none-linux-gnueabi"

; Function Attrs: norecurse nounwind optsize
define void @f(i32,i32,i32,i32,i32* %x4p, i32* %x5p, i32* %x6p) {
if.end:
  br label %while.body

while.body:
  %ll.0100 = phi i64 [ 0, %if.end ], [ %shr32, %while.body ]
  %add = add nuw nsw i64 %ll.0100, 0
  %add3 = add nuw nsw i64 %add, 0
  %shr = lshr i64 %add3, 32
  %conv7 = zext i32 %0 to i64
  %conv9 = zext i32 %1 to i64
  %add10 = add nuw nsw i64 %conv9, %conv7
  %add11 = add nuw nsw i64 %add10, %shr
  %shr14 = lshr i64 %add11, 32
  %conv16 = zext i32 %2 to i64
  %conv18 = zext i32 %3 to i64
  %add19 = add nuw nsw i64 %conv18, %conv16
  %add20 = add nuw nsw i64 %add19, %shr14
  %conv21 = trunc i64 %add20 to i32
  store i32 %conv21, i32* %x6p, align 4
  %shr23 = lshr i64 %add20, 32
  %x4 = load i32, i32* %x4p, align 4
  %conv25 = zext i32 %x4 to i64
  %x5 = load i32, i32* %x5p, align 4
  %conv27 = zext i32 %x5 to i64
  %add28 = add nuw nsw i64 %conv27, %conv25
  %add29 = add nuw nsw i64 %add28, %shr23
  %shr32 = lshr i64 %add29, 32
  br label %while.body
}


Referenced Bugs:

https://bugs.llvm.org/show_bug.cgi?id=35804
[Bug 35804] [meta] 6.0.0 Release Blockers
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