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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - Assertion `ARM::GPRRegClass.contains(DestReg, SrcReg) && "Thumb1 can only copy GPR registers"' failed."
href="https://bugs.llvm.org/show_bug.cgi?id=35836">35836</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>Assertion `ARM::GPRRegClass.contains(DestReg, SrcReg) && "Thumb1 can only copy GPR registers"' failed.
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>6.0
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>Windows NT
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>enhancement
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Backend: ARM
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>efriedma@codeaurora.org
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org, renato.golin@linaro.org, roger.ferreribanez@arm.com
</td>
</tr>
<tr>
<th>Blocks</th>
<td>35804
</td>
</tr></table>
<p>
<div>
<pre>I think this is a regression from r320355 ([ARM] Use ADDCARRY / SUBCARRY). It
looks like the SelectionDAG scheduler generates a schedule where an ADDS and an
ADC aren't adjacent, and tries to COPY cpsr to compensate. But we have no way
to lower that because we don't have access to MSR/MRS in Thumb1 mode, so we get
an assertion failure. Haven't really thought through the right way to fix
this.
Testcase (crashes with "llc test.ll"):
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv5e-none-linux-gnueabi"
; Function Attrs: norecurse nounwind optsize
define void @f(i32,i32,i32,i32,i32* %x4p, i32* %x5p, i32* %x6p) {
if.end:
br label %while.body
while.body:
%ll.0100 = phi i64 [ 0, %if.end ], [ %shr32, %while.body ]
%add = add nuw nsw i64 %ll.0100, 0
%add3 = add nuw nsw i64 %add, 0
%shr = lshr i64 %add3, 32
%conv7 = zext i32 %0 to i64
%conv9 = zext i32 %1 to i64
%add10 = add nuw nsw i64 %conv9, %conv7
%add11 = add nuw nsw i64 %add10, %shr
%shr14 = lshr i64 %add11, 32
%conv16 = zext i32 %2 to i64
%conv18 = zext i32 %3 to i64
%add19 = add nuw nsw i64 %conv18, %conv16
%add20 = add nuw nsw i64 %add19, %shr14
%conv21 = trunc i64 %add20 to i32
store i32 %conv21, i32* %x6p, align 4
%shr23 = lshr i64 %add20, 32
%x4 = load i32, i32* %x4p, align 4
%conv25 = zext i32 %x4 to i64
%x5 = load i32, i32* %x5p, align 4
%conv27 = zext i32 %x5 to i64
%add28 = add nuw nsw i64 %conv27, %conv25
%add29 = add nuw nsw i64 %add28, %shr23
%shr32 = lshr i64 %add29, 32
br label %while.body
}</pre>
</div>
</p>
<div id="referenced">
<hr style="border: 1px dashed #969696">
<b>Referenced Bugs:</b>
<ul>
<li>
[<a class="bz_bug_link
bz_status_NEW "
title="NEW - [meta] 6.0.0 Release Blockers"
href="https://bugs.llvm.org/show_bug.cgi?id=35804">Bug 35804</a>] [meta] 6.0.0 Release Blockers
</li>
</ul>
</div>
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