[llvm-bugs] [Bug 36252] New: [AMDGPU][MC][CODEGEN] Incorrect definition of GATHER4 opcodes

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=36252

            Bug ID: 36252
           Summary: [AMDGPU][MC][CODEGEN] Incorrect definition of GATHER4
                    opcodes
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: AMDGPU
          Assignee: unassignedbugs at nondot.org
          Reporter: dpreobrazhensky at luxoft.com
                CC: llvm-bugs at lists.llvm.org

Currently GATHER4 opcodes are defined in a way similar to other non-atomic MIMG
opcodes. Dst size depends on how many bits are set in DMask which can have any
4-bit value.

However, GATHER4 opcodes have a few differences from other MIMG instructions:
- DMask must have only one bit set to 1;
- Dst size is fixed:
  - for SI, CI and gfx8.0, dst size is 4 dwords.
  - for gfx8.1 and gfx9, dst size is 4 or 2 dwords depending on d16.

This difference affects:
- MC layer
- Codegen

-- 
You are receiving this mail because:
You are on the CC list for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-bugs/attachments/20180206/94b47cd7/attachment.html>