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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [AMDGPU][MC][CODEGEN] Incorrect definition of GATHER4 opcodes"
href="https://bugs.llvm.org/show_bug.cgi?id=36252">36252</a>
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<th>Summary</th>
<td>[AMDGPU][MC][CODEGEN] Incorrect definition of GATHER4 opcodes
</td>
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Windows NT
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: AMDGPU
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>dpreobrazhensky@luxoft.com
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</tr>
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<p>
<div>
<pre>Currently GATHER4 opcodes are defined in a way similar to other non-atomic MIMG
opcodes. Dst size depends on how many bits are set in DMask which can have any
4-bit value.
However, GATHER4 opcodes have a few differences from other MIMG instructions:
- DMask must have only one bit set to 1;
- Dst size is fixed:
- for SI, CI and gfx8.0, dst size is 4 dwords.
- for gfx8.1 and gfx9, dst size is 4 or 2 dwords depending on d16.
This difference affects:
- MC layer
- Codegen</pre>
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