[llvm-bugs] [Bug 39975] New: [DAGCombine] Missed truncate(extract()) -> extract(bitcast()) opportunities

via llvm-bugs llvm-bugs at lists.llvm.org
Wed Dec 12 05:17:35 PST 2018


            Bug ID: 39975
           Summary: [DAGCombine] Missed truncate(extract()) ->
                    extract(bitcast()) opportunities
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Common Code Generator Code
          Assignee: unassignedbugs at nondot.org
          Reporter: llvm-dev at redking.me.uk
                CC: andrea.dibiagio at gmail.com, craig.topper at gmail.com,
                    llvm-bugs at lists.llvm.org, spatel+llvm at rotateright.com

As mentioned in https://reviews.llvm.org/D55558

DAGCombine is very conservative at combining truncate + vector extracts, only
performing it before legalization:

Meaning we miss a change to improve:

define float @cvt(<2 x i64> %a0) nounwind {
  %1 = ashr <2 x i64> %a0, <i64 33, i64 33>
  %2 = extractelement <2 x i64> %1, i32 0
  %3 = sitofp i64 %2 to float
  ret float %3

llc -mcpu=btver2

cvt: # @cvt
  vpsrad $1, %xmm0, %xmm0
  vpshufd $245, %xmm0, %xmm0 # xmm0 = xmm0[1,1,3,3]
  vmovq %xmm0, %rax
  vcvtsi2ssl %eax, %xmm1, %xmm0
cvt2: # @cvt2
  vpsrad $1, %xmm0, %xmm0
  vpextrd $1, %xmm0, %eax
  vcvtsi2ssl %eax, %xmm1, %xmm0


We could just add a more aggressive combine to X86, but an alternative would be
some kind of 'isExtractInsertVectorIndexLegal(VT, int)' check to let the
existing general combine operate later.

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