[llvm-bugs] [Bug 39921] New: [X86] AVX2 should use an extract_subvector and phadd for the first step of a pairwise v8i32 addition reduction

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=39921

            Bug ID: 39921
           Summary: [X86] AVX2 should use an extract_subvector and phadd
                    for the first step of a pairwise v8i32 addition
                    reduction
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: craig.topper at gmail.com
                CC: craig.topper at gmail.com, llvm-bugs at lists.llvm.org,
                    llvm-dev at redking.me.uk, spatel+llvm at rotateright.com

For this IR I think we should use an extract subvector and a v4i32 phaddd for
the first step

define i32 @pairwise_reduction8i32(<8 x i32> %rdx, i32 %f1) {
  %rdx.shuf.0.0 = shufflevector <8 x i32> %rdx, <8 x i32> undef, <8 x i32> <i32
0, i32 2, i32 4, i32 6,i32 undef, i32 undef, i32 undef, i32 undef>
  %rdx.shuf.0.1 = shufflevector <8 x i32> %rdx, <8 x i32> undef, <8 x i32> <i32
1, i32 3, i32 5, i32 7,i32 undef, i32 undef, i32 undef, i32 undef>
  %bin.rdx = add <8 x i32> %rdx.shuf.0.0, %rdx.shuf.0.1
  %rdx.shuf.1.0 = shufflevector <8 x i32> %bin.rdx, <8 x i32> undef,<8 x i32>
<i32 0, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32
undef>
  %rdx.shuf.1.1 = shufflevector <8 x i32> %bin.rdx, <8 x i32> undef,<8 x i32>
<i32 1, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32
undef>
  %bin.rdx8 = add <8 x i32> %rdx.shuf.1.0, %rdx.shuf.1.1
  %rdx.shuf.2.0 = shufflevector <8 x i32> %bin.rdx8, <8 x i32> undef,<8 x i32>
<i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32
undef>
  %rdx.shuf.2.1 = shufflevector <8 x i32> %bin.rdx8, <8 x i32> undef,<8 x i32>
<i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32
undef>
  %bin.rdx9 = add <8 x i32> %rdx.shuf.2.0, %rdx.shuf.2.1

  %r = extractelement <8 x i32> %bin.rdx9, i32 0
  ret i32 %r
}


Instead we generate this

        vpshufd $232, %ymm0, %ymm1      # ymm1 = ymm0[0,2,2,3,4,6,6,7]
        vpermq  $232, %ymm1, %ymm1      # ymm1 = ymm1[0,2,2,3]
        vpshufd $237, %ymm0, %ymm0      # ymm0 = ymm0[1,3,2,3,5,7,6,7]
        vpermq  $232, %ymm0, %ymm0      # ymm0 = ymm0[0,2,2,3]
        vpaddd  %xmm0, %xmm1, %xmm0
        vpshufd $232, %xmm0, %xmm1      # xmm1 = xmm0[0,2,2,3]
        vpshufd $237, %xmm0, %xmm0      # xmm0 = xmm0[1,3,2,3]
        vpaddd  %ymm0, %ymm1, %ymm0
        vpshufd $229, %xmm0, %xmm1      # xmm1 = xmm0[1,1,2,3]
        vpaddd  %xmm1, %xmm0, %xmm0
        vmovd   %xmm0, %eax


That's 4 shuffles and vpaddd. But using vextracti128 and phaddd is only 3
shuffles on Intel hardware.

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