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<base href="https://bugs.llvm.org/">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [X86] AVX2 should use an extract_subvector and phadd for the first step of a pairwise v8i32 addition reduction"
href="https://bugs.llvm.org/show_bug.cgi?id=39921">39921</a>
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<th>Summary</th>
<td>[X86] AVX2 should use an extract_subvector and phadd for the first step of a pairwise v8i32 addition reduction
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>Windows NT
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>enhancement
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Backend: X86
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>craig.topper@gmail.com
</td>
</tr>
<tr>
<th>CC</th>
<td>craig.topper@gmail.com, llvm-bugs@lists.llvm.org, llvm-dev@redking.me.uk, spatel+llvm@rotateright.com
</td>
</tr></table>
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<pre>For this IR I think we should use an extract subvector and a v4i32 phaddd for
the first step
define i32 @pairwise_reduction8i32(<8 x i32> %rdx, i32 %f1) {
%rdx.shuf.0.0 = shufflevector <8 x i32> %rdx, <8 x i32> undef, <8 x i32> <i32
0, i32 2, i32 4, i32 6,i32 undef, i32 undef, i32 undef, i32 undef>
%rdx.shuf.0.1 = shufflevector <8 x i32> %rdx, <8 x i32> undef, <8 x i32> <i32
1, i32 3, i32 5, i32 7,i32 undef, i32 undef, i32 undef, i32 undef>
%bin.rdx = add <8 x i32> %rdx.shuf.0.0, %rdx.shuf.0.1
%rdx.shuf.1.0 = shufflevector <8 x i32> %bin.rdx, <8 x i32> undef,<8 x i32>
<i32 0, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32
undef>
%rdx.shuf.1.1 = shufflevector <8 x i32> %bin.rdx, <8 x i32> undef,<8 x i32>
<i32 1, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32
undef>
%bin.rdx8 = add <8 x i32> %rdx.shuf.1.0, %rdx.shuf.1.1
%rdx.shuf.2.0 = shufflevector <8 x i32> %bin.rdx8, <8 x i32> undef,<8 x i32>
<i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32
undef>
%rdx.shuf.2.1 = shufflevector <8 x i32> %bin.rdx8, <8 x i32> undef,<8 x i32>
<i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32
undef>
%bin.rdx9 = add <8 x i32> %rdx.shuf.2.0, %rdx.shuf.2.1
%r = extractelement <8 x i32> %bin.rdx9, i32 0
ret i32 %r
}
Instead we generate this
vpshufd $232, %ymm0, %ymm1 # ymm1 = ymm0[0,2,2,3,4,6,6,7]
vpermq $232, %ymm1, %ymm1 # ymm1 = ymm1[0,2,2,3]
vpshufd $237, %ymm0, %ymm0 # ymm0 = ymm0[1,3,2,3,5,7,6,7]
vpermq $232, %ymm0, %ymm0 # ymm0 = ymm0[0,2,2,3]
vpaddd %xmm0, %xmm1, %xmm0
vpshufd $232, %xmm0, %xmm1 # xmm1 = xmm0[0,2,2,3]
vpshufd $237, %xmm0, %xmm0 # xmm0 = xmm0[1,3,2,3]
vpaddd %ymm0, %ymm1, %ymm0
vpshufd $229, %xmm0, %xmm1 # xmm1 = xmm0[1,1,2,3]
vpaddd %xmm1, %xmm0, %xmm0
vmovd %xmm0, %eax
That's 4 shuffles and vpaddd. But using vextracti128 and phaddd is only 3
shuffles on Intel hardware.</pre>
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