[llvm-bugs] [Bug 35436] New: [AMDGPU][MC][GFX9] VGPR-offset should be 32 bits for global_* instructions

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https://bugs.llvm.org/show_bug.cgi?id=35436

            Bug ID: 35436
           Summary: [AMDGPU][MC][GFX9] VGPR-offset should be 32 bits for
                    global_* instructions
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: AMDGPU
          Assignee: unassignedbugs at nondot.org
          Reporter: dpreobrazhensky at luxoft.com
                CC: llvm-bugs at lists.llvm.org

AMD documentation describes two types of addressing supported by global_*
instructions:

• Memory_addr = VGPR-address + instruction offset.
• Memory_addr = SGPR-address + VGPR-offset + instruction offset.

Moreover, the documentation states that "VGPR-offset is always 32 bits".

See, for example, page 80 of Vega_Shader_ISA_28July2017.pdf

However, both SP3 and LLVM assemblers require a pair of registers for
VGPR-offset, for example:

global_store_dword v[1:2], v4, s[6:7] inst_offset:-1

Is this a bug in AMD documentation or should assembler be corrected?

Note that documentation requires 32-bit VGPR-offsets for scratch_* opcodes, and
this requirement is met by both assembler implementations.

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