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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [AMDGPU][MC][GFX9] VGPR-offset should be 32 bits for global_* instructions"
href="https://bugs.llvm.org/show_bug.cgi?id=35436">35436</a>
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<th>Summary</th>
<td>[AMDGPU][MC][GFX9] VGPR-offset should be 32 bits for global_* instructions
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: AMDGPU
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>dpreobrazhensky@luxoft.com
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<p>
<div>
<pre>AMD documentation describes two types of addressing supported by global_*
instructions:
• Memory_addr = VGPR-address + instruction offset.
• Memory_addr = SGPR-address + VGPR-offset + instruction offset.
Moreover, the documentation states that "VGPR-offset is always 32 bits".
See, for example, page 80 of Vega_Shader_ISA_28July2017.pdf
However, both SP3 and LLVM assemblers require a pair of registers for
VGPR-offset, for example:
global_store_dword v[1:2], v4, s[6:7] inst_offset:-1
Is this a bug in AMD documentation or should assembler be corrected?
Note that documentation requires 32-bit VGPR-offsets for scratch_* opcodes, and
this requirement is met by both assembler implementations.</pre>
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