[llvm-bugs] [Bug 35213] New: mrs ip, psr invalid operand for instruction

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=35213

            Bug ID: 35213
           Summary: mrs ip, psr invalid operand for instruction
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: ARM
          Assignee: unassignedbugs at nondot.org
          Reporter: lesliezhai at llvm.org.cn
                CC: llvm-bugs at lists.llvm.org

Hi LLVM developers,

$ /opt/llvm-svn/bin/llvm-mc -filetype=obj -triple=thumbv7m context_switch.S -o
context_switch.o
context_switch.S:7:10: error: invalid operand for instruction
        mrs ip, psr
                ^


context_switch.S  
https://github.com/jserv/mini-arm-os/blob/master/02-ContextSwitch-1/context_switch.S#L7


$ /opt/llvm-svn/bin/llvm-mc --version
LLVM (http://llvm.org/):
  LLVM version 6.0.0svn
  Optimized build.
  Default target: x86_64-redhat-linux
  Host CPU: sandybridge

  Registered Targets:
    aarch64    - AArch64 (little endian)
    aarch64_be - AArch64 (big endian)
    amdgcn     - AMD GCN GPUs
    arc        - ARC
    arm        - ARM
    arm64      - ARM64 (little endian)
    armeb      - ARM (big endian)
    avr        - Atmel AVR Microcontroller
    bpf        - BPF (host endian)
    bpfeb      - BPF (big endian)
    bpfel      - BPF (little endian)
    hexagon    - Hexagon
    lanai      - Lanai
    mips       - Mips
    mips64     - Mips64 [experimental]
    mips64el   - Mips64el [experimental]
    mipsel     - Mipsel
    msp430     - MSP430 [experimental]
    nvptx      - NVIDIA PTX 32-bit
    nvptx64    - NVIDIA PTX 64-bit
    ppc32      - PowerPC 32
    ppc64      - PowerPC 64
    ppc64le    - PowerPC 64 LE
    r600       - AMD GPUs HD2XXX-HD6XXX
    sparc      - Sparc
    sparcel    - Sparc LE
    sparcv9    - Sparc V9
    systemz    - SystemZ
    thumb      - Thumb
    thumbeb    - Thumb (big endian)
    x86        - 32-bit X86: Pentium-Pro and above
    x86-64     - 64-bit X86: EM64T and AMD64
    xcore      - XCore


But GNU cross-compile toolchain is able to work:
$ gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi-gcc -fno-common
-ffreestanding -O0 -gdwarf-2 -g3 -Wall -Werror -mcpu=cortex-m3 -mthumb
-Wl,-Tos.ld -nostartfiles  os.c startup.c context_switch.S -o os.elf

Regards,
Leslie Zhai

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