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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - mrs ip, psr invalid operand for instruction"
href="https://bugs.llvm.org/show_bug.cgi?id=35213">35213</a>
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<th>Summary</th>
<td>mrs ip, psr invalid operand for instruction
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
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<th>OS</th>
<td>Linux
</td>
</tr>
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<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>normal
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
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<th>Component</th>
<td>Backend: ARM
</td>
</tr>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>lesliezhai@llvm.org.cn
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
</tr></table>
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<pre>Hi LLVM developers,
$ /opt/llvm-svn/bin/llvm-mc -filetype=obj -triple=thumbv7m context_switch.S -o
context_switch.o
context_switch.S:7:10: error: invalid operand for instruction
mrs ip, psr
^
context_switch.S
<a href="https://github.com/jserv/mini-arm-os/blob/master/02-ContextSwitch-1/context_switch.S#L7">https://github.com/jserv/mini-arm-os/blob/master/02-ContextSwitch-1/context_switch.S#L7</a>
$ /opt/llvm-svn/bin/llvm-mc --version
LLVM (<a href="http://llvm.org/">http://llvm.org/</a>):
LLVM version 6.0.0svn
Optimized build.
Default target: x86_64-redhat-linux
Host CPU: sandybridge
Registered Targets:
aarch64 - AArch64 (little endian)
aarch64_be - AArch64 (big endian)
amdgcn - AMD GCN GPUs
arc - ARC
arm - ARM
arm64 - ARM64 (little endian)
armeb - ARM (big endian)
avr - Atmel AVR Microcontroller
bpf - BPF (host endian)
bpfeb - BPF (big endian)
bpfel - BPF (little endian)
hexagon - Hexagon
lanai - Lanai
mips - Mips
mips64 - Mips64 [experimental]
mips64el - Mips64el [experimental]
mipsel - Mipsel
msp430 - MSP430 [experimental]
nvptx - NVIDIA PTX 32-bit
nvptx64 - NVIDIA PTX 64-bit
ppc32 - PowerPC 32
ppc64 - PowerPC 64
ppc64le - PowerPC 64 LE
r600 - AMD GPUs HD2XXX-HD6XXX
sparc - Sparc
sparcel - Sparc LE
sparcv9 - Sparc V9
systemz - SystemZ
thumb - Thumb
thumbeb - Thumb (big endian)
x86 - 32-bit X86: Pentium-Pro and above
x86-64 - 64-bit X86: EM64T and AMD64
xcore - XCore
But GNU cross-compile toolchain is able to work:
$ gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi-gcc -fno-common
-ffreestanding -O0 -gdwarf-2 -g3 -Wall -Werror -mcpu=cortex-m3 -mthumb
-Wl,-Tos.ld -nostartfiles os.c startup.c context_switch.S -o os.elf
Regards,
Leslie Zhai</pre>
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