[llvm-bugs] [Bug 33011] New: MVN instruction "Upredictable" bit patterns incorrect

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https://bugs.llvm.org/show_bug.cgi?id=33011

            Bug ID: 33011
           Summary: MVN instruction "Upredictable" bit patterns incorrect
           Product: libraries
           Version: 4.0
          Hardware: PC
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: ARM
          Assignee: unassignedbugs at nondot.org
          Reporter: jtd at galois.com
                CC: llvm-bugs at lists.llvm.org

The MVN instructions in the TGEN data for ARM have all-zero Unpredictable
pattens, but the ARM architecture manual specifies some bits in MVN
instructions as expected to be zero but unpredictable otherwise.

ARM manual version: ARMv7-A and ARMv7-R edition, ARM DDI 0406C.b (ID072512)
Relevant sections: A8.8.116, A8.8.117

Instruction variants affected in LLVM ISA definition for ARM: MVNsr, MVNi,
MVNr.

For all of these variants, the ARM ARM specifies that bit positions [19:16]
should be zero and unpredictable otherwise. All variants in LLVM 4.0 declare
these to have no unpredictable bits.

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