<html>
<head>
<base href="https://bugs.llvm.org/">
</head>
<body><table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - MVN instruction "Upredictable" bit patterns incorrect"
href="https://bugs.llvm.org/show_bug.cgi?id=33011">33011</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>MVN instruction "Upredictable" bit patterns incorrect
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>4.0
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>All
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>normal
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Backend: ARM
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>jtd@galois.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
</tr></table>
<p>
<div>
<pre>The MVN instructions in the TGEN data for ARM have all-zero Unpredictable
pattens, but the ARM architecture manual specifies some bits in MVN
instructions as expected to be zero but unpredictable otherwise.
ARM manual version: ARMv7-A and ARMv7-R edition, ARM DDI 0406C.b (ID072512)
Relevant sections: A8.8.116, A8.8.117
Instruction variants affected in LLVM ISA definition for ARM: MVNsr, MVNi,
MVNr.
For all of these variants, the ARM ARM specifies that bit positions [19:16]
should be zero and unpredictable otherwise. All variants in LLVM 4.0 declare
these to have no unpredictable bits.</pre>
</div>
</p>
<hr>
<span>You are receiving this mail because:</span>
<ul>
<li>You are on the CC list for the bug.</li>
</ul>
</body>
</html>