[llvm-bugs] [Bug 32999] New: Missed vpadd combine opportunity

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=32999

            Bug ID: 32999
           Summary: Missed vpadd combine opportunity
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: ARM
          Assignee: unassignedbugs at nondot.org
          Reporter: zvi.rackover at intel.com
                CC: llvm-bugs at lists.llvm.org

This came up as a regression in ARM codegen in D32993.

For the following case,

define void @test(<16 x i8> *%cbcr, <4 x i16> *%X) nounwind ssp {
  %tmp = load <16 x i8>, <16 x i8>* %cbcr
  %tmp1 = zext <16 x i8> %tmp to <16 x i16>
  %tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <8 x i32> <i32 0,
i32 2, i32 4, i32 6, i32 undef, i32 undef, i32 undef, i32 undef>
  %tmp2a = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 0,
i32 1, i32 2, i32 3>
  %tmp3 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <8 x i32> <i32 1,
i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
  %tmp3a = shufflevector <8 x i16> %tmp3, <8 x i16> undef, <4 x i32> <i32 0,
i32 1, i32 2, i32 3>
  %add = add <4 x i16> %tmp2a, %tmp3a
  store <4 x i16> %add, <4 x i16>* %X, align 8
  ret void
}

llc -mtriple=arm-eabi -mattr=+neon  -o - -lower-interleaved-accesses=false

        vld1.64 {d16, d17}, [r0]
        vmovl.u8        q8, d16
        vuzp.16 q8, q9
        vadd.i16        d16, d16, d18
        vstr    d16, [r1]
        mov     pc, lr

This could be improved to:
        vld1.64 {d16, d17}, [r0]
        vmovl.u8        q8, d16
        vpadd.i16       d16, d16, d17
        vstr    d16, [r1]
        mov     pc, lr

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