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<base href="https://bugs.llvm.org/">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - Missed vpadd combine opportunity"
href="https://bugs.llvm.org/show_bug.cgi?id=32999">32999</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>Missed vpadd combine opportunity
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>Windows NT
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>enhancement
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Backend: ARM
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>zvi.rackover@intel.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
</tr></table>
<p>
<div>
<pre>This came up as a regression in ARM codegen in D32993.
For the following case,
define void @test(<16 x i8> *%cbcr, <4 x i16> *%X) nounwind ssp {
%tmp = load <16 x i8>, <16 x i8>* %cbcr
%tmp1 = zext <16 x i8> %tmp to <16 x i16>
%tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <8 x i32> <i32 0,
i32 2, i32 4, i32 6, i32 undef, i32 undef, i32 undef, i32 undef>
%tmp2a = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 0,
i32 1, i32 2, i32 3>
%tmp3 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <8 x i32> <i32 1,
i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
%tmp3a = shufflevector <8 x i16> %tmp3, <8 x i16> undef, <4 x i32> <i32 0,
i32 1, i32 2, i32 3>
%add = add <4 x i16> %tmp2a, %tmp3a
store <4 x i16> %add, <4 x i16>* %X, align 8
ret void
}
llc -mtriple=arm-eabi -mattr=+neon -o - -lower-interleaved-accesses=false
vld1.64 {d16, d17}, [r0]
vmovl.u8 q8, d16
vuzp.16 q8, q9
vadd.i16 d16, d16, d18
vstr d16, [r1]
mov pc, lr
This could be improved to:
vld1.64 {d16, d17}, [r0]
vmovl.u8 q8, d16
vpadd.i16 d16, d16, d17
vstr d16, [r1]
mov pc, lr</pre>
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