[llvm-bugs] [Bug 32371] New: shuffle (concat_vectors v4f64) hits assertion with AVX512

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=32371

            Bug ID: 32371
           Summary: shuffle (concat_vectors v4f64) hits assertion with
                    AVX512
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: zvi.rackover at intel.com
                CC: llvm-bugs at lists.llvm.org

Starting from r294774 the following test miscompiles:

llc -mcpu=skx

  define <8 x double> @foo2(<4 x double> %v) {
    %res = shufflevector <4 x double> %v, <4 x double> undef, <8 x i32>    
<i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
    ret <8 x double> %res
  }


llvm/lib/Target/X86/X86ISelLowering.cpp:9919: llvm::SDValue
lowerVectorShuffleAsBroadcast(const llvm::SDLoc &, llvm::MVT, llvm::SDValue,
llvm::SDValue, ArrayRef<int>, const llvm::X86Subtarget &, llvm::SelectionDAG
&): Assertion `SrcVT.getVectorNumElements() ==
BroadcastVT.getVectorNumElements() && "Unexpected vector num elements"' failed.

Here's the DAG at the time the assert fires:

SelectionDAG has 11 nodes:
  t0: ch = EntryToken
        t2: v4f64,ch = CopyFromReg t0, Register:v4f64 %vreg0
      t4: v8f64 = concat_vectors t2, undef:v4f64
    t6: v8f64 = vector_shuffle<2,2,2,2,2,2,2,2> t4, undef:v8f64
  t9: ch,glue = CopyToReg t0, Register:v8f64 %ZMM0, t6
  t10: ch = X86ISD::RET_FLAG t9, TargetConstant:i32<0>, Register:v8f64 %ZMM0,
t9:1

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