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    <head>
      <base href="https://bugs.llvm.org/">
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    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - shuffle (concat_vectors v4f64) hits assertion with AVX512"
   href="https://bugs.llvm.org/show_bug.cgi?id=32371">32371</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>shuffle (concat_vectors v4f64) hits assertion with AVX512
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>libraries
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>Windows NT
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>normal
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Backend: X86
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>zvi.rackover@intel.com
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>llvm-bugs@lists.llvm.org
          </td>
        </tr></table>
      <p>
        <div>
        <pre>Starting from r294774 the following test miscompiles:

llc -mcpu=skx

  define <8 x double> @foo2(<4 x double> %v) {
    %res = shufflevector <4 x double> %v, <4 x double> undef, <8 x i32>    
<i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
    ret <8 x double> %res
  }


llvm/lib/Target/X86/X86ISelLowering.cpp:9919: llvm::SDValue
lowerVectorShuffleAsBroadcast(const llvm::SDLoc &, llvm::MVT, llvm::SDValue,
llvm::SDValue, ArrayRef<int>, const llvm::X86Subtarget &, llvm::SelectionDAG
&): Assertion `SrcVT.getVectorNumElements() ==
BroadcastVT.getVectorNumElements() && "Unexpected vector num elements"' failed.

Here's the DAG at the time the assert fires:

SelectionDAG has 11 nodes:
  t0: ch = EntryToken
        t2: v4f64,ch = CopyFromReg t0, Register:v4f64 %vreg0
      t4: v8f64 = concat_vectors t2, undef:v4f64
    t6: v8f64 = vector_shuffle<2,2,2,2,2,2,2,2> t4, undef:v8f64
  t9: ch,glue = CopyToReg t0, Register:v8f64 %ZMM0, t6
  t10: ch = X86ISD::RET_FLAG t9, TargetConstant:i32<0>, Register:v8f64 %ZMM0,
t9:1</pre>
        </div>
      </p>


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