[llvm-bugs] [Bug 35713] New: [X86] VPERMW assigned to wrong port in SKX sheduler model

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=35713

            Bug ID: 35713
           Summary: [X86] VPERMW assigned to wrong port in SKX sheduler
                    model
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: craig.topper at gmail.com
                CC: llvm-bugs at lists.llvm.org

I would be very surprised if VPERMW is on port0. Seems more likely on port5
like every other shuffle. The memory form is using port23 and port5 in the
scheduler model.

def SKXWriteResGroup72 : SchedWriteRes<[SKXPort0]> {
  let Latency = 6;
  let NumMicroOps = 2;
  let ResourceCycles = [2];
}
...
def: InstRW<[SKXWriteResGroup72], (instregex "VPERMWZ128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup72], (instregex "VPERMWZ256rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup72], (instregex "VPERMWZrr(b?)(k?)(z?)")>;

-- 
You are receiving this mail because:
You are on the CC list for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-bugs/attachments/20171221/3dd83604/attachment.html>