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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [X86] VPERMW assigned to wrong port in SKX sheduler model"
href="https://bugs.llvm.org/show_bug.cgi?id=35713">35713</a>
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<th>Summary</th>
<td>[X86] VPERMW assigned to wrong port in SKX sheduler model
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: X86
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>craig.topper@gmail.com
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<p>
<div>
<pre>I would be very surprised if VPERMW is on port0. Seems more likely on port5
like every other shuffle. The memory form is using port23 and port5 in the
scheduler model.
def SKXWriteResGroup72 : SchedWriteRes<[SKXPort0]> {
let Latency = 6;
let NumMicroOps = 2;
let ResourceCycles = [2];
}
...
def: InstRW<[SKXWriteResGroup72], (instregex "VPERMWZ128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup72], (instregex "VPERMWZ256rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup72], (instregex "VPERMWZrr(b?)(k?)(z?)")>;</pre>
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