[llvm-bugs] [Bug 34046] New: [DAGCombiner] Failure to recognise i8 and i16 rotation patterns

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=34046

            Bug ID: 34046
           Summary: [DAGCombiner] Failure to recognise i8 and i16 rotation
                    patterns
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Common Code Generator Code
          Assignee: unassignedbugs at nondot.org
          Reporter: llvm-dev at redking.me.uk
                CC: llvm-bugs at lists.llvm.org, spatel+llvm at rotateright.com

The presence of additional truncs/exts prevents DAGCombiner::MatchRotate from
recognising i8/i16 rotations:

#include <stdint.h>

uint32_t rotate32(uint32_t v, size_t shift) {
  shift &= 31;
  v = ( v << shift ) | ( v >> ( 32 - shift ) );
  return v;
}

uint16_t rotate16(uint16_t v, size_t shift) {
  shift &= 15;
  v = ( v << shift ) | ( v >> ( 16 - shift ) );
  return v;
}

uint8_t rotate8(uint8_t v, size_t shift) {
  shift &= 7;
  v = ( v << shift ) | ( v >> ( 8 - shift ) );
  return v;
}

-O3 -march=btver2

define i32 @rotate32(i32, i64) {
  %3 = and i64 %1, 31
  %4 = trunc i64 %3 to i32
  %5 = shl i32 %0, %4
  %6 = sub nsw i64 32, %3
  %7 = trunc i64 %6 to i32
  %8 = lshr i32 %0, %7
  %9 = or i32 %8, %5
  ret i32 %9
}

define zeroext i16 @rotate16(i16 zeroext, i64) {
  %3 = and i64 %1, 15
  %4 = zext i16 %0 to i32
  %5 = trunc i64 %3 to i32
  %6 = shl i32 %4, %5
  %7 = sub nsw i64 16, %3
  %8 = trunc i64 %7 to i32
  %9 = lshr i32 %4, %8
  %10 = or i32 %9, %6
  %11 = trunc i32 %10 to i16
  ret i16 %11
}

define zeroext i8 @rotate8(i8 zeroext, i64) {
  %3 = and i64 %1, 7
  %4 = zext i8 %0 to i32
  %5 = trunc i64 %3 to i32
  %6 = shl i32 %4, %5
  %7 = sub nsw i64 8, %3
  %8 = trunc i64 %7 to i32
  %9 = lshr i32 %4, %8
  %10 = or i32 %9, %6
  %11 = trunc i32 %10 to i8
  ret i8 %11
}

rotate32:
  movl %esi, %ecx
  roll %cl, %edi
  movl %edi, %eax
  retq

rotate16:
  andl $15, %esi
  movl %edi, %eax
  movl %esi, %ecx
  shll %cl, %eax
  movl $16, %ecx
  subl %esi, %ecx
  shrl %cl, %edi
  orl %eax, %edi
  movl %edi, %eax
  retq

rotate8:
  andl $7, %esi
  movl %edi, %eax
  movl %esi, %ecx
  shll %cl, %eax
  movl $8, %ecx
  subl %esi, %ecx
  shrl %cl, %edi
  orl %eax, %edi
  movl %edi, %eax
  retq

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