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<base href="https://bugs.llvm.org/">
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<body><table border="1" cellspacing="0" cellpadding="8">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [DAGCombiner] Failure to recognise i8 and i16 rotation patterns"
href="https://bugs.llvm.org/show_bug.cgi?id=34046">34046</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>[DAGCombiner] Failure to recognise i8 and i16 rotation patterns
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>Windows NT
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>enhancement
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Common Code Generator Code
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>llvm-dev@redking.me.uk
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org, spatel+llvm@rotateright.com
</td>
</tr></table>
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<div>
<pre>The presence of additional truncs/exts prevents DAGCombiner::MatchRotate from
recognising i8/i16 rotations:
#include <stdint.h>
uint32_t rotate32(uint32_t v, size_t shift) {
shift &= 31;
v = ( v << shift ) | ( v >> ( 32 - shift ) );
return v;
}
uint16_t rotate16(uint16_t v, size_t shift) {
shift &= 15;
v = ( v << shift ) | ( v >> ( 16 - shift ) );
return v;
}
uint8_t rotate8(uint8_t v, size_t shift) {
shift &= 7;
v = ( v << shift ) | ( v >> ( 8 - shift ) );
return v;
}
-O3 -march=btver2
define i32 @rotate32(i32, i64) {
%3 = and i64 %1, 31
%4 = trunc i64 %3 to i32
%5 = shl i32 %0, %4
%6 = sub nsw i64 32, %3
%7 = trunc i64 %6 to i32
%8 = lshr i32 %0, %7
%9 = or i32 %8, %5
ret i32 %9
}
define zeroext i16 @rotate16(i16 zeroext, i64) {
%3 = and i64 %1, 15
%4 = zext i16 %0 to i32
%5 = trunc i64 %3 to i32
%6 = shl i32 %4, %5
%7 = sub nsw i64 16, %3
%8 = trunc i64 %7 to i32
%9 = lshr i32 %4, %8
%10 = or i32 %9, %6
%11 = trunc i32 %10 to i16
ret i16 %11
}
define zeroext i8 @rotate8(i8 zeroext, i64) {
%3 = and i64 %1, 7
%4 = zext i8 %0 to i32
%5 = trunc i64 %3 to i32
%6 = shl i32 %4, %5
%7 = sub nsw i64 8, %3
%8 = trunc i64 %7 to i32
%9 = lshr i32 %4, %8
%10 = or i32 %9, %6
%11 = trunc i32 %10 to i8
ret i8 %11
}
rotate32:
movl %esi, %ecx
roll %cl, %edi
movl %edi, %eax
retq
rotate16:
andl $15, %esi
movl %edi, %eax
movl %esi, %ecx
shll %cl, %eax
movl $16, %ecx
subl %esi, %ecx
shrl %cl, %edi
orl %eax, %edi
movl %edi, %eax
retq
rotate8:
andl $7, %esi
movl %edi, %eax
movl %esi, %ecx
shll %cl, %eax
movl $8, %ecx
subl %esi, %ecx
shrl %cl, %edi
orl %eax, %edi
movl %edi, %eax
retq</pre>
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