[llvm-bugs] [Bug 32769] New: MachineCSE eliminates CMP instruction even when there are other CMPs in the same BB.

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=32769

            Bug ID: 32769
           Summary: MachineCSE eliminates CMP instruction even when there
                    are other CMPs in the same BB.
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Common Code Generator Code
          Assignee: unassignedbugs at nondot.org
          Reporter: pftbest at gmail.com
                CC: llvm-bugs at lists.llvm.org

Created attachment 18339
  --> https://bugs.llvm.org/attachment.cgi?id=18339&action=edit
bug.ll

This can be reproduced on MSP430 target, IR is in the attachment.

After isel we have this basic block:

BB#0: derived from LLVM BB %start
    Live Ins: %R12 %R13 %R14 %R15
        %vreg3<def> = COPY %R15; GR16:%vreg3
        %vreg2<def> = COPY %R14; GR16:%vreg2
        %vreg1<def> = COPY %R13; GR16:%vreg1
        %vreg0<def> = COPY %R12; GR16:%vreg0
        CMP16rr %vreg1, %vreg3, %SR<imp-def>; GR16:%vreg1,%vreg3
        %vreg4<def> = COPY %SR; GR16:%vreg4
        %vreg5<def> = MOV16ri 1; GR16:%vreg5
        %vreg6<def,tied1> = BIC16rr %vreg5<tied0>, %vreg4, %SR<imp-def,dead>;
GR16:%vreg6,%vreg5,%vreg4
        CMP16rr %vreg0, %vreg2, %SR<imp-def>; GR16:%vreg0,%vreg2
        %vreg7<def> = COPY %SR; GR16:%vreg7
        %vreg8<def,tied1> = BIC16rr %vreg5<tied0>, %vreg7, %SR<imp-def,dead>;
GR16:%vreg8,%vreg5,%vreg7
        CMP16rr %vreg1, %vreg3, %SR<imp-def,dead>; GR16:%vreg1,%vreg3
        JCC <BB#2>, 0, %SR<imp-use>
    Successors according to CFG: BB#1(?%) BB#2(?%)

then after CSE it looks like this:

BB#0: derived from LLVM BB %start
    Live Ins: %R12 %R13 %R14 %R15
        %vreg3<def> = COPY %R15; GR16:%vreg3
        %vreg2<def> = COPY %R14; GR16:%vreg2
        %vreg1<def> = COPY %R13; GR16:%vreg1
        %vreg0<def> = COPY %R12; GR16:%vreg0
        CMP16rr %vreg1, %vreg3, %SR<imp-def>; GR16:%vreg1,%vreg3
        %vreg4<def> = COPY %SR; GR16:%vreg4
        %vreg5<def> = MOV16ri 1; GR16:%vreg5
        %vreg6<def,tied1> = BIC16rr %vreg5<tied0>, %vreg4, %SR<imp-def,dead>;
GR16:%vreg6,%vreg5,%vreg4
        CMP16rr %vreg0, %vreg2, %SR<imp-def>; GR16:%vreg0,%vreg2
        %vreg7<def> = COPY %SR; GR16:%vreg7
        %vreg8<def,tied1> = BIC16rr %vreg5<tied0>, %vreg7, %SR<imp-def,dead>;
GR16:%vreg8,%vreg5,%vreg7
        JCC <BB#2>, 0, %SR<imp-use>
    Successors according to CFG: BB#1(?%) BB#2(?%)

CSE removed the last CMP instruction because it's the same as the first one.
But there is also another CMP in between them.

-- 
You are receiving this mail because:
You are on the CC list for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-bugs/attachments/20170424/b9dd44da/attachment.html>