[llvm-bugs] [Bug 30544] New: LLVM doesn't support codegen for PowerPC SPE unit

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=30544

            Bug ID: 30544
           Summary: LLVM doesn't support codegen for PowerPC SPE unit
           Product: libraries
           Version: trunk
          Hardware: Other
                OS: FreeBSD
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: PowerPC
          Assignee: unassignedbugs at nondot.org
          Reporter: chmeeedalf at gmail.com
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

Thought it's deprecated and not included in any newer designs, the PowerPC
Signal Processing Engine is included in cores used in several NXP/Freescale
SoCs.

The SPE is a combination of DSP-like and vector-unit-like instructions, along
with 64-bit registers that overlap the GPRs (all 32 GPRs are sized to 64-bit,
with the upper 32-bits only accessible from SPE instructions).  This is also
the only source of hardware floating point support in the Freescale e500v1 and
e500v2 cores.

I did check earlier, and there is disassembly support for these instructions,
but no assembler, and no codegen support.

-- 
You are receiving this mail because:
You are on the CC list for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-bugs/attachments/20160927/7ea3202f/attachment.html>