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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - LLVM doesn't support codegen for PowerPC SPE unit"
href="https://llvm.org/bugs/show_bug.cgi?id=30544">30544</a>
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<th>Summary</th>
<td>LLVM doesn't support codegen for PowerPC SPE unit
</td>
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>Other
</td>
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<th>OS</th>
<td>FreeBSD
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>Backend: PowerPC
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>chmeeedalf@gmail.com
</td>
</tr>
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<th>Classification</th>
<td>Unclassified
</td>
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<p>
<div>
<pre>Thought it's deprecated and not included in any newer designs, the PowerPC
Signal Processing Engine is included in cores used in several NXP/Freescale
SoCs.
The SPE is a combination of DSP-like and vector-unit-like instructions, along
with 64-bit registers that overlap the GPRs (all 32 GPRs are sized to 64-bit,
with the upper 32-bits only accessible from SPE instructions). This is also
the only source of hardware floating point support in the Freescale e500v1 and
e500v2 cores.
I did check earlier, and there is disassembly support for these instructions,
but no assembler, and no codegen support.</pre>
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</p>
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