[llvm-bugs] [Bug 27943] New: powerpc: "Bad machine code: Using an undefined physical register"

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=27943

            Bug ID: 27943
           Summary: powerpc: "Bad machine code: Using an undefined
                    physical register"
           Product: new-bugs
           Version: 3.8
          Hardware: PC
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: vtjnash at gmail.com
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

Created attachment 16441
  --> https://llvm.org/bugs/attachment.cgi?id=16441&action=edit
bugpoint-reduced powerpc64le peephole optimization bug

The attached code asserts when compiling with llc (no extra arguments needed),
in what appears to be a failure to update the imp-def register list during
instruction replacement by Peephole Optimizations.

The observed error message is:

```
*** Bad machine code: Using an undefined physical register ***
- function:    julia_gcd_50079
- basic block: BB#4 L14 (0x7fae4202aa98)
- instruction: %vreg121<def> = COPY
- operand 1:   %CR0
LLVM ERROR: Found 1 machine code errors.
```

Before peephole optimizations, the SUBFC8 is used:

```
# *** IR Dump After Machine code sinking ***:
        %vreg24<def> = SUBFC8 %vreg18<kill>, %vreg12<kill>, %CARRY<imp-def>;
G8RC_and_G8RC_NOX0:%vreg24 G8RC:%vreg18,%vreg12
```

Afterwards, the `SUBFC8o` alias is used instead (this replacement is correct):

```
# *** IR Dump After Peephole Optimizations ***:
        %vreg24<def> = SUBFC8o %vreg18<kill>, %vreg12<kill>, %CARRY<imp-def>;
G8RC_and_G8RC_NOX0:%vreg24 G8RC:%vreg18,%vreg12
        %vreg35<def> = COPY %CR0<kill>; CRRC:%vreg35
```

However, this replacement should have added `%CR0<imp-def>`, but didn't. (the
PPCInstrInfo.td entry for `multiclass XOForm_1rc` of which this instruction is
an alias of an instance reflects this correctly.)

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